今日的行程：
辦公室：10:00 - 19:30
讀書室：19:30 - 20:00

正片開始

Form PC-relatvie Address Instruction

// ADR <Xd>, <label>        Xd = label address (pc-relative +- 1MB)
// ADRP <Xd>, <label>       Xd = label address Align 4K (pc-relative +- 4GB)

align 3
my_data1:
    .dword 0x8a
adrp_test:
    adr x0, my_data1        // x0 == 0x806a8
    ldr x1, [x0]            // x1 == 0x8a
    adr x2, my_data1        // x2 == 0x80000 (align 4K)
    ldr x3, [x2]            // x3 == xxxxxxx

LDR pseudo-instruction & ADR

LDR pseudo-instruction load 位址是絕對位址，ADR load 位址是相對於 PC 的位址，所以:

• if (link address == load address); then LDR == ADR
• if (link address != load address); then LDR != ADR, LDR load link address (might be VA: 0xffff_0000_0008_0000), ADR load PC-relative address, use ADR

Exclusive Memory Access Instruction (chapter 20)

// LDXR, LDXP
LDXR <Xt>, [Xn]
LDXP <Xt1>, <Xt2>, [Xn]
// STXR, STXP
STXR <Ws>, <Xt>, [Xn]
STXP <Ws>, <Xt1>, <Xt2> [Xn]

Exception Handling Instruction (chapter 21)

SVC #imm    // trap to OS (EL1)
HVC #imm    // trap to hypervisor (EL2)
SMC #imm    // trap to secure monitor (EL3)

System Register Access Instruction

MRS <Xn>, <system reg>        // read system reg
MSR <system reg>, <Xn>        // write system reg

Memory Barrier Instruction (chapter 18)

DMB: Data Memory Barrier
DSB: Data Synchronization Barrier
ISB: Instruction Synchronization Barrier

LDAR: Load-acquire 
STLR: Store-release

總結

• ARM64 指令大致上就先讀到這囉！！
• RISC-V 有提供類似的指令
  • Exclusive memory access: LR, SC
  • Exception handling: ecall
  • System Register access: csrr, csrw, csrrw
  • Memory Barrier: fence, fence.i, sfence.vma