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2022 iThome 鐵人賽
DAY 24
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Software Development

超簡單的 Verilog 入門講解系列 第 24 篇

[Day 24] Verilog E-1 難度丁 P2海域的消血4 - Rs232訊號協議 讀取第一個資料 b0~b7 ( 設計輸出3 )

14th鐵人賽
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狀態3 b0 的設定

昨天講到狀態3 b0 的設定

https://ithelp.ithome.com.tw/upload/images/20221007/2013586215KQE6nukJ.png


3:
    begin  
        if(Count_clk >= 287 ) begin
               Count_clk<=0;
               Out1[0] <=Data;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
        end
    end

狀態4 b1 的設定

其實到 狀態4 一樣是

  1. 移動 1個 bin → 287 clk

  2. 讀到的 Data 付值到 Out1的第1位

  3. 收到後移動到 State 5

  4. 移動 1個 bin → 287 clk

 if(Count_clk >= 287 ) begin
      Count_clk<=0;
end
else begin
     Count_clk<=Count_clk+1;
end
  1. 讀到的 Data 付值到 Out1的第1位
 if(Count_clk >= 287 ) begin
      Count_clk<=0; 
      Out1[0] <=Data;//讀到的 Data 付值到 Out1的第1位
end
else begin
     Count_clk<=Count_clk+1;
end
  1. 收到後移動到 State 5
 if(Count_clk >= 287 ) begin
      Count_clk<=0;
      Out1[0] <=Data;
      State1 <= 5; //收到後移動到 State 5
end
else begin
     Count_clk<=Count_clk+1;
end

狀態5 ~ 10 → b2 ~ b7 的設定

https://ithelp.ithome.com.tw/upload/images/20221007/20135862aQhs1F4Itl.png

直接寫結果吧:

module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;
// 所以 Out1 是個 reg
reg[7:0] Out1;

reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin
   //設定為 Reg 就要馬上給他初始化
   Out1<=0;
   
   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0;
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin

            State1 <= 2;

          end
    end  
    
    2:
    begin
         if(Count_clk >= 143 ) begin
    
               Count_clk<=0;
               State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end
    
    3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[0] <=Data;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    4:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[1] <=Data;
               State1 <= 5;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    5:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[2] <=Data;
               State1 <= 6;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    6:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[3] <=Data;
               State1 <= 7;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    7:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[4] <=Data;
               State1 <= 8;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    8:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[5] <=Data;
               State1 <= 9;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    9:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[6] <=Data;
               State1 <= 10;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    10:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[7] <=Data;
               State1 <= 11;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    11:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               // 讀到的 Data  付值到 Out1的第0位
               Out1[0] <=Data;
               State1 <= 12;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    
    
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

告訴使用者可以收訊號了

如何告訴使用者可以收資料呢 En_out 變成 1 阿

https://ithelp.ithome.com.tw/upload/images/20221007/20135862Y7C8O9kSqL.png

1.設定 En_out 為reeg
2.En_out 變成 1
3.輸出0.5個 bin 的時間好了 144 clk
4.關掉 En_out 變成 0
5.跳回狀態1
6.狀態1 En_out 初始 0

1.設定 En_out 為reeg

老樣子En_out是 Reg
reg En_out

定義 Reg 就初始化


if( ~reset1) begin
   //設定為 Reg 就要馬上給他初始化
   Out1<=0;
   En_out <=0;
   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0;
   State1 <=0;
end

2.En_out 變成 1

    12:
    begin  
        En_out <= 1;
    end

3.輸出0.5個 bin 的時間好了 144 clk

    12:
    begin  
        if(Count_clk >= 287 ) begin
            Count_clk<=0;
        end
        else begin
        
            En_out <= 1; //En_out 變成 1
            
            Count_clk<=Count_clk+1;
        end
    end

4.關掉 En_out 變成 0

    12:
    begin  
        if(Count_clk >= 287 ) begin
            Count_clk<=0;
            En_out <= 0; 
        end
        else begin
        
            En_out <= 1; 
            
            Count_clk<=Count_clk+1;
        end
    end

5.跳回狀態1

    12:
    begin  
        if(Count_clk >= 287 ) begin
            Count_clk<=0;
            En_out <= 0; 
            State1 <= 1;
        end
        else begin
        
            En_out <= 1; 
            
            Count_clk<=Count_clk+1;
        end
    end

6.狀態1 En_out 初始 0

    1:
    begin
          if(~Data_Previous1 & Data1 ) begin
            En_out <= 0; 
            State1 <= 2;

          end
    end

放進程式碼吧

module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;
// 所以 Out1 是個 reg
reg[7:0] Out1;
// 所以 En_out 是個 reg
reg En_out;

reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin
   //設定為 Reg 就要馬上給他初始化
   Out1<=0;
   
   //設定為 Reg 就要馬上給他初始化
   En_out <= 0; 
   
   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0;
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin
            En_out <= 0; 
            State1 <= 2;

          end
    end  
    
    2:
    begin
         if(Count_clk >= 143 ) begin
    
               Count_clk<=0;
               State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end
    
    3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[0] <=Data;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    4:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[1] <=Data;
               State1 <= 5;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    5:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[2] <=Data;
               State1 <= 6;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    6:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[3] <=Data;
               State1 <= 7;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    7:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[4] <=Data;
               State1 <= 8;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    8:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[5] <=Data;
               State1 <= 9;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    9:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[6] <=Data;
               State1 <= 10;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    10:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               Out1[7] <=Data;
               State1 <= 11;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    11:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               // 讀到的 Data  付值到 Out1的第0位
               Out1[0] <=Data;
               State1 <= 12;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    
    12:
    begin  
        if(Count_clk >= 287 ) begin
            Count_clk<=0;
            En_out <= 0; 
            State1 <= 1;
        end
        else begin
        
            En_out <= 1; 
            
            Count_clk<=Count_clk+1;
        end
    end  
    
    
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

明天再把 default 寫一寫 就大蓋完成了


上一篇
[Day 23] Verilog E-1 難度丁 P2海域的消血3 - Rs232訊號協議 讀取第一個資料 b0 ( 設計輸出2 )
下一篇
[Day 25] Verilog E-1 難度丁 P2海域的消血5 - Rs232訊號協議 default ( 設計輸出4 )
系列文
超簡單的 Verilog 入門講解 共 30 篇
  1. 26
    [Day 26] Verilog E-1 難度丁 P2海域的斬殺1 - Rs232訊號協議 TB設計(TB的初始框架)
  2. 27
    [Day 27] Verilog E-1 難度丁 P2海域的斬殺2 - Rs232訊號協議 TB設計2(計算輸入資料的 clk數量)
  3. 28
    [Day 28] Verilog E-1 難度丁 P2海域的斬殺3 - Rs232訊號協議 TB設計3(初始化輸入數據)
  4. 29
    [Day 29] Verilog E-1 難度丁 P2海域的斬殺4 - Rs232訊號協議 TB設計4(設計右移)
  5. 30
    [Day 30] Verilog E-1 難度丁 - P2 結尾
完整目錄
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