這顆 CPU 實作主要是為了承接接下來的 dual issue 和 OOO
而且在 arithmetic 指令也有不同長短
stage 設計跟只有 ALU 的會不太一樣

1. Fetch
2. Decode
3. Dispatch / operand read
4. Issue
5. Execute
6. Writeback / completion
7. Retire

Normal ALU command:
flowchart LR
D[Decode ALU op] --> O[Capture operands]
O --> IQ[Issue Queue]
IQ -->|oldest and ready| S[Scheduler]
S --> R[Issue / EX]
R --> A[Available ALU]
A -->|1-cycle result| W[Writeback Arbiter]
W --> E[EX / WB]
E --> C[Completion Queue + IQ wakeup]
C -->|when oldest| T[Retire and update register file]

Mul/Div command:
flowchart LR
D[Decode RV32M op] --> O[Capture operands]
O --> IQ[Issue Queue]
IQ -->|oldest, operands ready,\nM unit available| S[Scheduler]
S --> R[Issue / EX]
R --> M[MUL / DIV unit]
M --> P[32 iterative steps]
P --> C[Sign/result correction]
C -->|result valid| W[Writeback Arbiter]
W --> E[EX / WB]
E --> Q[Completion Queue + IQ wakeup]
Q -->|when oldest| T[Retire and update register file]

git link with tag: https://github.com/hsufit/TINY5_OOO/tree/ithome2026_D6