既然每級 pipeline 都拆完了
回過頭來實作 SystemC CPU Model 吧
新增了一組 test case，同樣使用這 5 道指令來確認
重新算過 cycle 數量，有對上 RTL 實作

    addi x1, x0, 6
    addi x2, x0, 7
    add  x3, x1, x2
    mul  x4, x1, x2
    add  x5, x3, x4

Run log:

Thu Sep 24 10:45 PM [~/TINY5_OOO]
root@HSU-PC:[TINY5_OOO]<main>$ ./run_docker.sh
Docker image tiny5-dev already exists.
Do you want to rebuild it? (y/N): y
Rebuilding Docker image: tiny5-dev
DEPRECATED: The legacy builder is deprecated and will be removed in a future release.
            Install the buildx component to build images with BuildKit:
            https://docs.docker.com/go/buildx/
...
root@47cd07e4b588:/workspace# cd riscv_emulator/
root@47cd07e4b588:/workspace/riscv_emulator# ./run.sh
-- The CXX compiler identification is GNU 11.4.0
-- Detecting CXX compiler ABI info
...
[100%] Linking CXX executable rv32im_tests
[100%] Built target rv32im_tests
Internal ctest changing into directory: /workspace/riscv_emulator/build
Test project /workspace/riscv_emulator/build
    Start 1: rv32im_arithmetic
1/2 Test #1: rv32im_arithmetic ................   Passed    0.01 sec
    Start 2: instruction_memory_protocol
2/2 Test #2: instruction_memory_protocol ......   Passed    0.00 sec

100% tests passed, 0 tests failed out of 2

Total Test time (real) =   0.02 sec

        SystemC 3.0.2-Accellera --- Sep 17 2026 05:03:41
        Copyright (c) 1996-2025 by all Contributors,
        ALL RIGHTS RESERVED
[PASS] ADD/MUL sequence [normal] cycles=66 retired=5
[PASS] ADD/MUL sequence [stalled] cycles=82 retired=5
[PASS] RV32I register arithmetic [normal] cycles=79 retired=14
[PASS] RV32I register arithmetic [stalled] cycles=139 retired=14
[PASS] RV32I immediate arithmetic [normal] cycles=54 retired=9
[PASS] RV32I immediate arithmetic [stalled] cycles=94 retired=9
[PASS] RV32M multiply and divide [normal] cycles=302 retired=10
[PASS] RV32M multiply and divide [stalled] cycles=314 retired=10
[PASS] RV32M division corner cases [normal] cycles=207 retired=10
[PASS] RV32M division corner cases [stalled] cycles=219 retired=10
[PASS] hard-wired x0 [normal] cycles=19 retired=2
[PASS] hard-wired x0 [stalled] cycles=31 retired=2
[PASS] unsupported opcode [normal] cycles=10 retired=0
[PASS] unsupported opcode [stalled] cycles=18 retired=0
[PASS] truncated instruction [normal] cycles=9 retired=0
[PASS] truncated instruction [stalled] cycles=13 retired=0
All RV32IM arithmetic tests passed

Info: /OSCI/SystemC: Simulation stopped by user.

git link with tag: https://github.com/hsufit/TINY5_OOO/tree/ithome2026_D10